1. Field of the Invention
This invention relates to a capacitor wherein a lower electrode made of conductive film opposes an upper electrode through a capacitive insulating film and is applied to a large capacity DRAM (Dynamic RAM).
2. Description of the Related Art
In the DRAM, a capacitor composing a memory cell must possess an electric storage capacity larger than a predetermined level in order to assure a predetermined or higher read-out voltage and refresh interval and prevent a soft error even if the memory cell area is reduced because of miniaturization and increased capacity.
Conventionally, to increase the electric storage capacity without increasing the area of the capacitor, the SiO film as the capacitive insulating film was thinned and if thinning of the SiO.sub.2 film reached its limit, an ONO film having a higher dielectric constant than the SiO.sub.2 film was utilized as the capacitive insulating film. Further, application of such high dielectric constant insulating films as a Ta.sub.2 O.sub.5 film, a BST film, an STO film or the like are considered.
As a concrete proposal for increasing the electric storage capacity without increasing a plane area of the capacitor, Mr. Youichi Miyasaka, Basic Research Center, NEC announced "A possibility of BST series thin film for DRAM" at ULSI high dielectric constant thin film technology forum '95 (Feb. 3, 1995, Tokyo Garden Palace).
In the related arts, a first conventional example in which as shown in FIG. 1, the lower electrode was formed in a cylinder shape so that electricity was stored in its external side wall and internal side wall as well and a second conventional example in which as shown in FIGS. 2a and 2b, the lower electrode was formed in double cylinder shape so as to allow storage of electricity on a wider side wall are considered.
Assume that the external dimensions of the lower electrode in the first conventional example shown in FIG. 1 are L, W, and H and the thickness of the conductive film forming the lower electrode is d, internal dimensions L.sub.1, W.sub.1, H.sub.1 are as follows: EQU L.sub.1 =L-2d, W.sub.1 =W-2d, H.sub.1 =H-d.
Thus, the surface area S of the lower electrode in the first conventional example is; EQU S=2H(L+W)+2H.sub.1 (L.sub.1 +W.sub.1)+LW
Assuming that the dimensions of respective parts of the lower electrode in the second conventional example shown in FIGS. 2a and 2b are as shown in Figure, following can be obtained. EQU L.sub.1 =L-2d, W.sub.1 =W-2d, H.sub.1 =H-d EQU L.sub.2 =L-4d, W.sub.2 =W-4d, H.sub.2 =H-2d EQU L.sub.3 =L-6d, W.sub.3 =W-6d
Thus, the surface area S of the lower electrode in the second conventional example is;
S=2H(L+W)+2H.sub.1 (L.sub.1 +W.sub.1)+LW+2H.sub.1 (L.sub.2 +W.sub.2)+2H.sub.2 (L.sub.2 +W.sub.3)
This is larger than the first conventional example by only last two terms, thus it is more advantageous for increasing the electric storage capacity.
However if the memory cell area is reduced because of miniaturization and increased capacity of the DRAM so that the plane area of the lower electrode of the capacitor is also reduced, in the second conventional example shown in FIGS. 7a and 7b, a smaller one of L3 and W3 becomes 0. Consequently, a cylinder inside is crushed, so that a double cylinder type cannot be realized. Thus in such a case, conventionally, the first conventional example shown in FIG. 1 was utilized.